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PRELIMINARY
MX98745
100 BASE-TX/FX REPEATER CONTROLLER
1.0 FEATURES
* IEEE 802.3u D5 repeater and management compatible * Support 7 TX/FX ports and 1 universal port (TX or MII port selectable) * Support 8-scale utilization and collision rate LED display * Asynchronous Expansion port clock supported for easily stackable application * Separate jabber and partition state machines for each port * On-chip elasticity buffer for PHY signal re-timing to the MX98745 clock source * Contents of internal register loaded from EEPROM * PCS/MAC type MII interface selectable * CMOS device features high integration and low power with a signle +5V supply
2.0 GENERAL DESCRIPTION
The MX98745, Second generation 100 Mb/s TX/FX Hub Controller (XRC II), is designed specifically to meet the needs of today's high speed Fast Ethernet networking systems. The MX98745 is fully IEEE 802.3u D5 clause 27 repeater compatible. Difference from MX98741, which provides 8 dedicated TX/FX ports and 3 MII ports, MX98745 support 7 dedicated TX/FX ports and one programmble TX/FX/MII port. Whenever MII port is programmed, MX98745 also supports the flexibility to make user can easily select PCS or MAC type MII for system application. With this programmable MII interface, user can easily connect MX98745 to MX98742 (Bridge), or T4 transceiver. Or user can use this programmable MII interface to connect to either MAC or PCS type data transceiver. All contents of internal registers are loaded from EEPROM in MX98745. If system application prefers default setting instead of using contents from EEPROM, EEPROM operation can be disabled by setting EECONF to low. This feature faciliates system modulization application. 8 scale of utilization LED is also provided by MX98745. They are 1%, 3%, 5%, 10%, 20%, 40%, 60% and 80+%. The defination for utiliztion is Mbs Received/100 Mb within one second sampling period. Meanwhile, RX/LINK, Partition, Isolation and Collision status are also provided through LED display. A great improvement in MX98745 (compared to MX98741) is that it also provides "synchronous expansion port data transfer mode" to make stackable design more easier.
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MX98745
3.0 BLOCK DIAGRAMS
MDC
MDIO LSCLK SIGDET[7:0]
Jabber Clock Generator RESEL Port 0 5B RX/ Port 0 4B RX SCRCTRL Repeater Core & Control/Status Registers Port 0 5B RX/ Port 0 4B RX TDAT0[4:0] TXCLK (MII Only) RDAT0[4:0] RSCLK0
Port 7 RX Relative FUN Port 7 Relative FUN
RDAT7[4:0] RSCLK7
TDAT7[4:0]
Expansion Port Function
Utilization/ Status LED Display FUN
EDACT JAMI EDAT[4:0] EPCLK JAMO EDENL EDCRS ANYACT LED[8:0]
LDSEL[2:0]
Figure 3-1 Block Diagram forMX98745
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4.0 PIN CONFIGURATION
GND RDAT30 RDAT31 RDAT32 RDAT33 RDAT34 GND TDAT30 TDAT31 TDAT32 TDAT33 TDAT34 GND RSCLK4 SIGDET4 VDD RDAT40 RDAT41 RDAT42 RDAT43 RDAT44 TDAT40 TDAT41 TDAT42 TDAT43 TDAT44 GND RSCLK5 SIGDET5 RDAT50 RDAT51 RDAT52 RDAT53 RDAT54 TDAT50 TDAT51 TDAT52 TDAT53 TDAT54 GND 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 VDD SIGDET3 RSCLK3 TDAT24 TDAT23 TDAT22 TDAT21 TDAT20 VDD RDAT24 RDAT23 RDAT22 RDAT21 RDAT20 GND SIGDET2 RSCLK2 VDD TDAT14 TDAT13 TDAT12 TDAT11 TDAT10 GND RDAT14 RDAT13 RDAT12 RDAT11 RDAT10 SIGDET1 RSCLK1 MON LED7/PHY4 LED6/PHY3 LED5/PHY2 LED4/PHY1 LED3/PHY0 LED2/TXMII LED1/PMSEL GND
GND RSCLK6 SIGDET6 RDAT60 RDAT61 RDAT62 RDAT63 RDAT64 TDAT60 TDAT61 TDAT62 TDAT63 TDAT64 GND RSCLK7 SIGDET7 GND RDAT70 RDAT71 RDAT72 RDAT73 RDAT74 VDD TDAT70 TDAT71 TDAT72 TDAT73 TDAT74 VDD LSCLK IBMON TSEL TEST XCOLED SCRCTRL RESETL COL MDO MDIO VDD
MX98745
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 VDD LED0/EECLK/PARSEL LDS2/ED0 GND LDS1/EDI LSD0/EECONF LEDEN VDD EECS EDACT ANYACT GND EDENL EDCRS JAM1 JAM0 EPCLK EDAT4 EDAT3 EDAT2 EDAT1 EDAT0 GND TXEN CRS GND TXCLK TDAT04/TXER TDAT03/TXD3 TDAT02/TXD2 TDAT01/TXD1 TDAT00/TXD0 EDAT04/RXER RDAT03/RXD3 RDAT02/RXD2 RDAT01/RXD1 RDAT00/RXD0 SIGDET0/RXDV RSCLK0 VDD
Figure 4-1 Pin Configuration for XRCII
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5.0 PIN DESCRIPTION
A. MX Data Transceiver (Am78965/Am78966 or MC68836), 98 pins PAD # 24-28 9-13 155-159 142-146 128-132 113-117 98-102 30 Name TDAT[7:1][0:4] I/O O, TTL Description Transmit Data. These five outputs are 5B encoded transmit data sym bols, driven at the rising edge of LSCLK. TDAT4 is the Most Significant Bit.
LSCLK
I, TTL I, TTL
18-22 4-8 150-154 137-141 122-126 107-111 92-96 15,2 148,134 118,104 90,42 16,3, 149,135, 119,105, 91 31
RDAT[7:1][0:4]
Local Synchrnous Clock. This pin supplies the frequency reference to the MX98745 within same HUB. It should be driven by a crystalcontrolled 25M clock source. Receive Data. These 5 bit parallel data symbol from transceiver are latched by the rising edge of RSCLK of each port. RDAT4 is the Most Significant Bit.
RSCLK[7:0]
I, TTL
Recovered Symbol Clock. This is a 25 MHz clock, which is derived from the clock synchronization PLL circuit.
SIGDET[7:1]
I, TTL
Signal Detect. This signal indicates that the received signal is above the detection threshold and will be used for the link test state machine.
Monitor
I, TTL
Monitor Mode. Internal Pulldown. When this pin is set to one, LED display pins LED[9:0] will be changed to monitor mode.
Table 5-1 Pin Description for XRCII
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B. Expansion Port, 12 pins PAD # 65 Name JAMO I/O O, CMOS I, TTL I, Sche I/O, TTL I/O, TTL O, CMOS I, Sche O, CMOS Description Forced Jam Out. Active High. The OR'd forced jam signals controlled by Carrier Integrity Monitor of each port. If collision occurs inside the XRC II (exclude JAMI), this pin is also asserted. Forced Jam Input. Active High. Asserted by external arbitor, and XRCII will generate JAM patterns to all its ports whenever this signal is validate more than 40 ns. This signal is filtered by LSCLK for 40ns internally. Enable Expansion Data. Active Low. Asserted by an external arbitor. XRC II will not drive data onto EDAT until this pin is asserted. Assertion time less than 40ns will not be recognized by XRC II. Expansion Data. Bidirectional 5 bit-wide data. By default, EDAT is an input. An external arbitor coordinates multiple devices on EDAT. Expansion port Data Clock. This clock will be outputed by XRCII along with the EDAT[4:0]. Another module of XRCII should use this signal as expansion port data input clock. Any Activity. Active High. When XRCII tries to release data onto EDAT, this pin will be asserted by XRC II. Expansion Data Carrier Sense. When this pin is asserted, XRC II will recognize that there is activity on expansion port data bus EDAT and perform corresponding activity within XRCII itself. Expansion Data Activity. When XRCII detects that EDENL is asserted by external arbitor, it will assert EDACT high. System application can use this signal to control the data bus flow of EDAT.
66
JAMI
68
EDENL
63-59 64
EDAT[4:0] EPCLK
70 67
ANYACT EDCRS
71
EDACT
Table 5-1 Pin Description for XRC II (Continued)
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C. Universal Port (UP), 14 pins PAD # Name 43 SIGDET0/ RXDV I/O I, TTL Description Signal Detect/Receive Data Valid. When TXMII (pin 84) is detected high during power on reset, This pin works as Signal detect in 5B data mode. When TXMII is low, this pin is output and works as RXDV in MII mode. This signal remains asserted through the whole frame, starting with the start-of-frame delimiter and excluding any end-of-frame deliminter Receive Data[3:0]. No matter TXMII's value is, these four pins work as the receive data both in TX mode and MII mode. Receive data is synchronous to RSCLK0's rising edge. Receive Data Bit 4/Receive Data Error. When TXMII is detected as 1, this pin works as the MSB of RDAT0[4:0]. When MII mode is selected, this pin is RXER and synchronous to RSCLK0's rising edge. Carrier Sense. In PCS Mode, synchronous to TXCLK. This pin is asserted when (1) the receiving medium is not idle, or (2) the transmitting medium is not idle in the half-duplex mode. In MAC mode (PMSEL is low), this pin is input. Transmit Enable. This pin is output and synchronous to the TXCLK's rising edge whenever valid data is presented on TXD[3:0] Transmit Data. No matter TXMII's value is, these four pins work as the transmit data both in TX mode and MII mode. In TX mode, TDAT is synchronous to LSCLK rising edge. In MII mode, TXD[0:3] is synchronous to TXCLK rising edge. Transmit Data Bit 4/Transmit ERROR. When TXMII is set to one, this pin work as the MSB of TDAT of port 0. When TXMII is low, This pin acts as TXEN and is synchronous to the TXCLK's rising edge. When TXER is asserted for one or more than one TXCLK period while TXEN is also asserted, one or more"HALT " symbols will present at TXD[3:0]. Collision. This signal is asserted if both the receiving media and TXEN are active. When PCS type MII is selected, this pin is output from XRCII and indicates that there is collision within the XRCII. When PMSEL is 0, COL is input to XRCII and indicates that there is collision on the receiving port. Transmit Clock. 25M Hz clock. TXD[3:0], TXEN, TXER are synchronous to this clock's rising edge. In PCS type MII (PMSEL is 1), CRS and COL are also synchronous to this clock's rising edge.
44-47
RDAT0[0:3]/ RXD[0:3] RDAT04/ RXER CRS
I, TTL I, TTL I/O, TTL O, CMOS O, CMOS
48
56
57 49-52
TXEN TDAT[0:3]/ TXD[0:3]
53
TDAT04/ TXER
O, CMOS
37
COL
I/O, CMOS
54
TXCLK
I/O, CMOS
Table 5-1 Pin Description for XRCII (Continued)
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MX98745
D. Management, 2 pins PAD # 38 39 Name MDC MDIO I/O I, TTL I/O, TTL Description Management Data Clock. The timing reference for MDIO. The minumum high and low times are 200 ns each. Management Data Input/Output. A bi-directional signal. The selection of input/output direction is based on IEEE802.3u management functions (Section 22.2.4).
E. Test/Miscellaneous, 5 pins PAD # 33 32 34 35 Name TEST TSEL XCOLED SCRCTRL I/O I I O, LED I, TTL Description Test. Industrial test pin. Set to 0 for normal operation. When programmed to logic 1, XRC II is in test mode. Test Select. Used by industrial test. Internal Pulldown. Set to 0 for normal operation. Collision LED. Active low. When there is collision within the XRC II, XCOLED will be on for 80ms and off for 20ms. Scrambler Control. Active High. When this pin is set to 0. All TX port will be set to descramble mode, i.e. contents of register #17 will be disabled. When this pin is set to 1. Each port's scrambler/descrambler is controller by corre sponding bit in register #17. Internally pullup. Reset. Active Low. Will be filtered by LSCLK within the MX98745. Internal Bus Monitor. In house debugging usage. Internally pull down.
36 31
RESETL IBMON
I, Sche I, TTL
Table 5-1 Pin Description for XRC II (Continued)
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F. LED Display/EEPROM Interface, 14 pins PAD # Name 74 LEDEN I/O O, Description Led Output Enable. When LEDEN is asserted high, it means that varuous internal CMOS status is shown on LED[7:0] according to the value on LDS[2:0] LED Output Select. LDS0 is internally pulldown and value on LDS0 will be latched internally by MX98745 at the rising edge of RESETL as the value of EECONF. Value on LDS1 will act as EEPROM Data Input signal during EEPROM loading operation (after power on reset and EECONF is set to 1) and LDS2 will be data output from EEPROM. When EECONF is low, EEPROM operation will be disabled. After power on reset, LDS[2:0] work as the select pins of LED[7:0] output. The following are corresponding definition LDS2 LDS1 LDS0 0 0 1 Link/Receive 0 1 0 Isolation 0 1 1 Partition 1 0 0 Utilization 1 0 1 Collision Rate LED 0/EEPROM Clock/Partition Select. Value on this pin will be latched by MX98745 at the rising edge of RESETL as the value of Partition Select (PARSEL). When EECONF is set to 1, this pin will work as EEPROM clock pin and output by MX98745 after power on reset. When EEPROM operation is enabled, internal repeater function will be disabled until contents in EEPROM is loaded into MX98745. After EEPROM operation is completed, this pin will display port 0's Receivee/Link, Partition, Isolation status and indicates 10% Network utilization and 3% collision rate according to the value of LDS[2:0]. LED 1/PCS & MAC type MII Select. When Power on reset, value on this pin will be latched at the rising edge of RESETL and be the value of PMSEL which can program the universal port (port 0) to PCS or MAC type MII interface. In normal operation (after power on reset), this pin will display port 1's Receivee/Link, Partition, Isolation status and indicates 20% Network utilization and 6% collision rate according to the value on LDS[2:0]
78, 76, 75
LDS2/EDO, LDS1/EDI, LDS0/EECONF
I/O, TTL
79
LEDO/, EECK/, PARSEL
I/O TTL
82
LED1/PMSEL
I/O, TTL
Table 5-1 Pin Description for XRC II (Continued)
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F. LED Display (Continued) PAD # 83 Name LED2/ TXMII I/O I/O, TTL Description LED 2/Port0 TX/MII mode Select. When Power on reset, value on this pin will be latched at the rising edge of RESETL and be the value of TXMII which can program the universal port (port 0) to TX mode (5B interface) or MII mode (4B) interface. When TXMII is set to 1, Port 0 of XRC II will be programmed to TX mode and PMSEL will be disabled. In normal operation (after power on reset), this pin will display port 2's Receivee/Link, Partition, Isolation status and indicates 30% Network utilization and 9% collision rate according to the value on LDS[2:0] LED 3/Physical Address 0. Value on LED3 will be latched at the rising edge of RESET as the setting of Device physical address 0. If EECONF is set to 1, PHY0 will be overwritten by the contents of EEPROM. After EEPROM operation is completed (in case EECONF is set to 1), this pin will display port 3's Receivee/Link, Partition, Isolation status and indicates 10% Network utilization and 8% collision rate according to the value on LDS[2:0] LED 4/Physical Address 1. Value on LED4 will be latched at the rising edge of RESETL as the physical address 1 of MX98745. If EECONF is set, Physical address will be overwritten by the value from EEPROM. After EEPROM operation is completed, this pin will display port 4's Receivee/ Link, Partition, Isolation status and indicates 20% Network utilization and 10% collision rate according to the value on LDS[2:0]. LED 5/Physical Address 2. Value on LED5 will be latched at the rising edge of RESETL as the physical address 2 of MX98745. If EECONF is set, Physical address will be overwritten by the value from EEPROM. After EEPROM operation is completed, this pin will display port 5's Receivee/ Link, Partition, Isolation status and indicates 40% Network utilization and 13% collision rate according to the value on LDS[2:0]. LED 6/Physical Address 3. Value on LED6 will be latched at the rising edge of RESETL as the physical address 3 of MX98745. If EECONF is set, Physical address will be overwritten by the value from EEPROM. After EEPROM operation is completed, this pin will display port 6's Receivee/ Link, Partition, Isolation status and indicates 60% Network utilization and 15% collision rate according to the value on LDS[2:0].
84
LED3/ PHY0
I/O, TTL
85
LED4/ PHY1
I/O, TTL
86
LED5/ PHY2
I/O, TTL
87
LED6/ PHY3
I/O, TTL
Table 5-1 Pin Description for XRC II (Continued)
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F. LED Display (Continued) PAD # 88 Name LED7/ PHY4 I/O I/O, TTL Description LED 7/Physical Address 4. Value on LED7 will be latched at the rising edge of RESETL as the physical address 4 of MX98745. If EECONF is set, Physical address will be overwritten by the value from EEPROM. After EEPROM operation is completed, this pin will display port 7's Receivee/ Link, Partition, Isolation status and indicates 80+% Network utilization and 20+% collision rate according to the value on LDS[2:0]. EEPROM Chip Select. Output by MX98745 when EECONF is set and EEPROM operation is activated by MX98745. Monitor. Value on this pin will be latched at the rising edge of RESETL. When programmed to high, internal state machines's states will be outputed to this pin serially for debugging usage. For normal operation, left unconnected.
72 89
EECS MON
O, CMOS I/O, TTL
G. Power/Ground Pins PAD # 1,14, 17,55, 58,69, 77,81, 97,106, 121,127, 133,147, 160 23,29, 41,73, 80,103, 112,120, 136, Name GND I/O Description Ground.
VDD
5V Power Supply.
Table 5-1 Pin Description for XRC II (Continued)
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MX98745
6.0 FUNCTIONAL AND OPERATION DESCRIPTION
6.1 All TX MODE SELECTED
EEPROM
XRC
Arb
XRC
DT& PMD Port 0
DT& PMD Port 7
DT& PMD Port 8
DT& PMD Port 15
Figure 6-1 Pure TX Mode operation for XRC II
6.2 TX AND MII MIXED MODE
EEPROM
Arbitor
XRC
XRC
MII or FX
DT& PMD Port 7
DT& PMD Port 8
DT& PMD Port 15
Figure 6-2 TX/MII Mixed Mode operation for XRC II
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6.3 INTERNAL REGISTERS All the registers can be accessed through MII's MDC and MDIO. Although XRC II connects to multiple 100-TX PHY's, they are all identical. Each XRC has only one PHY address as defined by PHY[4:0] pins (which will be latched by the rising edge of RESETL, and will be overwritten by the contents of EEPROM whenever EECONF is set to 1). If multiple XRC's are on the same MDIO bus, each of them should have different PHY address. Other non-XRC PHY devices (e.g. T4) are also allowed to be managed with the same management interface as long as PHY address of each device is distinct. Register 0 and 1 are Command and Status registers which specified in [1]. Additional registers provided by MX98745 is located from address 16 to 31 (decimal value). Port Control Registers are located from address #16 to address #20. These control registers include port reset control register (#16), Port Scremabler control register (#17), Port Enable Control Register (#18), Isolation Disable Control Register (#19) and Partition Disable Control Register (#20). Port Status Registers are located from address #25 to address #29. These registers include Link Status Register (#25), Partition Status Register (#26), Elastic Buffer Status Register (#27), Jabber Status Register (#28) and Isolation Status Register (#29). Register #31 is Configuration Register. Value latched at the rising edge of RESETL will be stored in this register. Value on this register will be overwritten by contents of EEPROM in case EECONF is set to 1 except PMSEL and TXMII which will be affected only by hardwire setting.
A. Command Register (register #0) (R/W) Bit(s) 0.15 Name Reset Description 1 : PHY reset. A 240ns reset pulse will be generated to reset XRC internal logic. 0 : normal operation. 1 : enable loopback mode. 0 : disable loopback mode. The default setting is 0. Forced to 1 and indicate 100 Mb/s. Write 0 to this bit has no effect. Forced to 0 and indicate that Auto-Negotiation process is disable. Write 1 to this bit has no effect. 1 : power down. COCLK and TXCLK for each port will be disabled. Clock for Management Block will keep running. During Power down, all state machines will be reset to its default state. 0 : normal operation. 1 : electrically Isolate PHY from MII 0 : normal operation R/W R/W SC R/W
0.14
Loop Back
0.13 0.12
Speed Selection Auto-Negotiation Enable
R R R/W R/W
0.11
Power Down
0.10
Isolate
R/W
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Bit(s) 0.9 Name Restart Auto-Negotiation Duplex Mode Description R/W Forced to 0 and indicate that Auto-Negotiation process is R disable. Write 1 to this bit has no effect. Forced to 0 and indicate that only Half R Duplex is available. Write 1 to this bit has no effect. 1 : enable COL signal test. The PHY will assert the COL R/W signal within 5120 ns in response to the assertion of TXEN. While this bit is set to one, the PHY will deassert the COL signal within 40 ns in respons to the deassertion of TXEN. 0 : normal operation. Set to 0 after power on reset. Value 0 will be read when one tries to read these bits. R Table 6-1 Control Register Bit Definition B. Status Register (register #1) (R) Bit(s) 1.15 1.14 1.13 1.12 1.11 1.10:6 1.5 1.4 1.3 1.2 1.1 1.0 Name 100BASE-T4 100BASE-X Full Duplex 100BASE-X Half Duplex 10 Mb/s Full Duplex 10 Mb/s Half Duplex Reserved Auto-Negotiation Remote Fault Auto-Negotiation Ability Link Status Jabber Detect Extended Capability Description Forced to 0 and indicates that XRC is not able to perform 100BASE-T4. Forced to 0 and indicates that XRC is not able to perform 100BASE-X Fill Duplex. Forced to 1 and indicates that XRC is able to perform 100BASE-X Half Duplex. Forced to 0 and indicates that XRC is not able to perform 10 Mb/s Full Duplex. Forced to 0 and indicates that XRC is not able to perform 10 Mb/s Half Duplex. Value 0 will be released by XRC when read. Forced to 0. Complete Forced to 0. Forced to 0. R/W R R R R R R R R R
0.8
0.7
Collision Test
0.6:0
Reserved
1 : All ports are link up. R 0 : Any port is link fail. Will be set to 1 after this port is read. 1 : Jabber condition in any port is detected. R 0 : No Jabber condition detected for all ports Forced to 1. R Table 6-2 Status Register Bit Definition
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C. Port Reset Register (register #16) (R/W) Bit(s) 16.15:8 16.7 Name Reserved ResetP7 Description Ignored when read. 1 : reset Port 7's Logic. 0 : not reset Port 7's Logic. Power on low. 1 : reset Port 6's Logic. 0 : not reset Port 6's Logic. Power on low. 1 : reset Port 5's Logic. 0 : not reset Port 5's Logic. Power on low. 1 : reset Port 4's Logic. 0 : not reset Port 4's Logic. Power on low. 1 : reset Port 3's Logic. 0 : not reset Port 3's Logic. Power on low. 1 : reset Port 2's Logic. 0 : not reset Port 2's Logic. Power on low. 1 : reset Port 1's Logic. 0 : not reset Port 1's Logic. Power on low. 1 : reset Port 0's Logic. 0 : not reset Port 0's Logic. Power on low. R/W R
16.6
ResetP6
R/W
16.5
ResetP5
R/W
16.4
ResetP4
R/W
16.3
ResetP3
R/W
16.2
ResetP2
R/W
16.1
ResetP1
R/W
16.0
ResetP0
R/W
Table 6-3 Port Reset Register Bit Definition Each bit will not clear to 0 automatically whenever it is set to 1. To ensure the MX98745 works properly, one should write 0 back to Port reset register after written 1 to corresponding bit.
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D. Scrambler Control Register (register #17) (R/W) Bit(s) 17.15:8 Name Reserved Description Write any value to these bits have no effect. Written value will be released onto MDIO whenever Read Command is issued 1 : Enable Scrambler/Descrambler at Port 7 0 : Disable Scrambler/Descrambler at Port 7 The default value after power on is 1. 1 : Enable Scrambler/Descrambler at Port 6 0 : Disable Scrambler/Descrambler at Port 6 The default value after power on is 1. 1 : Enable Scrambler/Descrambler at Port 5 0 : Disable Scrambler/Descrambler at Port 5 The default value after power on is 1. 1 : Enable Scrambler/Descrambler at Port 4 0 : Disable Scrambler/Descrambler at Port 4 The default value after power on is 1. 1 : Enable Scrambler/Descrambler at Port 3 0 : Disable Scrambler/Descrambler at Port 3 The default value after power on is 1. 1 : Enable Scrambler/Descrambler at Port 2 0 : Disable Scrambler/Descrambler at Port 2 The default value after power on is 1. 1 : Enable Scrambler/Descrambler at Port 1 0 : Disable Scrambler/Descrambler at Port 1 The default value after power on is 1. 1 : Enable Scrambler/Descrambler at Port 0 0 : Disable Scrambler/Descrambler at Port 0 The default value after power on is 1. R/W R/W
17.7
ScrenP7
R/W
17.6
ScrenP6
R/W
17.5
ScrenP5
R/W
17.4
ScrenP4
R/W
17.3
ScrenP3
R/W
17.2
ScrenP2
R/W
17.1
ScrenP1
R/W
17.0
ScrenP0
R/W
Table 6-4 Scrambler Control Register Bit Definition
Note : When SCRCTRL is set to 0, contents of this register will be disabled.
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E. Port Enable Control Register (register #18) (R/W) (Continued) Bit(s) 18.15:8 Name Reserved Description Write any value to these bits have no effect. Written value will be released onto MDIO whenever Read Command is issued 1 : Enable RX/TX functions at Port 7. 0 : Disable RX/TX functions at Port 7. The default value after power on is 1. 1 : Enable RX/TX functions at Port 6. 0 : Disable RX/TX functions at Port 6. The default value after power on is 1. 1 : Enable RX/TX functions at Port 5. 0 : Disable RX/TX functions at Port 5. The default value after power on is 1. 1 : Enable RX/TX functions at Port 4. 0 : Disable RX/TX functions at Port 4. The default value after power on is 1. 1 : Enable RX/TX functions at Port 3. 0 : Disable RX/TX functions at Port 3. The default value after power on is 1. 1 : Enable RX/TX functions at Port 2. 0 : Disable RX/TX functions at Port 2. The default value after power on is 1. 1 : Enable RX/TX functions at Port 1. 0 : Disable RX/TX functions at Port 1. The default value after power on is 1. 1 : Enable RX/TX functions at Port 0. 0 : Disable RX/TX functions at Port 0. The default value after power on is 1. R/W R/W
18.7
EnP7
R/W
18.6
EnP6
R/W
18.5
EnP5
R/W
18.4
EnP4
R/W
18.3
EnP3
R/W
18.2
EnP2
R/W
18.1
EnP1
R/W
18.0
EnP0
R/W
Table 6-5 Port Enable Control Register Bit Definition
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MX98745
F. Isolation Disable Register (register #19) (R/W) Bit(s) 19.15:8 Name Reserved Description Write any value to these bits have no effect. Written value will be released onto MDIO whenever Read Command is issued 1 : Port 7 Isolation function is disabled 0 : Port 7 Isolation function is not disabled. The default value is 0 after reset. 1 : Port 6 Isolation function is disabled 0 : Port 6 Isolation function is not disabled. The default value is 0 after reset. 1 : Port 5 Isolation function is disabled 0 : Port 5 Isolation function is not disabled. The default value is 0 after reset. 1 : Port 4 Isolation function is disabled 0 : Port 4 Isolation function is not disabled. The default value is 0 after reset. 1 : Port 3 Isolation function is disabled 0 : Port 3 Isolation function is not disabled. The default value is 0 after reset. 1 : Port 2 Isolation function is disabled 0 : Port 2 Isolation function is not disabled. The default value is 0 after reset. 1 : Port 1 Isolation function is disabled 0 : Port 1 Isolation function is not disabled. The default value is 0 after reset. 1 : Port 0 Isolation function is disabled 0 : Port 0 Isolation function is not disabled. The default value is 0 after reset. R/W R/W
19.7
ISODIS7
R/W
19.6
ISODIS6
R/W
19.5
ISODIS5
R/W
19.4
ISODIS4
R/W
19.3
ISODIS3
R/W
19.2
ISODIS2
R/W
19.1
ISODIS1
R/W
19.0
ISODIS0
R/W
Table 6-6 Isolation Disable Register Bit Definition
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MX98745
G. Partition Disable Register (register #20) (R/W) Bit(s) 20.15:8 Name Reserved Description Write any value to these bits have no effect. Written value will be released onto MDIO whenever Read Command is issued 1 : Port 7 Parition function is disbled. 0 : Port 7 Partition function is not disabled. The default value is 0 after reset. 1 : Port 6 Parition function is disbled. 0 : Port 6 Partition function is not disabled. The default value is 0 after reset. 1 : Port 5 Parition function is disbled. 0 : Port 5 Partition function is not disabled. The default value is 0 after reset. 1 : Port 4 Parition function is disbled. 0 : Port 4 Partition function is not disabled. The default value is 0 after reset. 1 : Port 3 Parition function is disbled. 0 : Port 3 Partition function is not disabled. The default value is 0 after reset. 1 : Port 2 Parition function is disbled. 0 : Port 2 Partition function is not disabled. The default value is 0 after reset. 1 : Port 1 Parition function is disbled. 0 : Port 1 Partition function is not disabled. The default value is 0 after reset. 1 : Port 0 Parition function is disbled. 0 : Port 0 Partition function is not disabled. The default value is 0 after reset. R/W R/W
20.7
PTNDIS7
R/W
20.6
PTNDIS6
R/W
20.5
PTNDIS5
R/W
20.4
PTNDIS4
R/W
20.3
PTNDIS3
R/W
20.2
PTNDIS2
R/W
20.1
PTNDIS1
R/W
20.0
PTNDIS0
R/W
Table 6-7 Partition Disable Register Bit Definition (Continued)
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MX98745
H. Link Status Register (register #25) (R) Bit(s) 25.15:8 25.7 Name Reserved LinkP7 Description Always 0. 1 : Link Status is OK at port 7 0 : Link Status is Fail at Port 7 Status is updated at every LSCLK clock. 1 : Link Status is OK at port 6 0 : Link Status is Fail at Port 6 Status is updated at every LSCLK clock. 1 : Link Status is OK at port 5 0 : Link Status is Fail at Port 5 Status is updated at every LSCLK clock. 1 : Link Status is OK at port 4 0 : Link Status is Fail at Port 4 Status is updated at every LSCLK clock. 1 : Link Status is OK at port 3 0 : Link Status is Fail at Port 3 Status is updated at every LSCLK clock. 1 : Link Status is OK at port 2 0 : Link Status is Fail at Port 2 Status is updated at every LSCLK clock. 1 : Link Status is OK at port 1 0 : Link Status is Fail at Port 1 Status is updated at every LSCLK clock. 1 : Link Status is OK at port 0 0 : Link Status is Fail at Port 0 Status is updated at every LSCLK clock. R/W R R
25.6
LinkP6
R
25.5
LinkP5
R
25.4
LinkP4
R
25.3
LinkP3
R
25.2
LinkP2
R
25.1
LinkP1
R
25.0
LinkP0
R
Table 6-8 Link Status Register Bit Definition
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MX98745
I. Partition Status Register (register #26) (R) Bit(s) 26.15:8 26.7 Name Reserved PartP7 Description Always 0. 1 : Port 7 has been partitioned 0 : Port 7 has not been partitioned Status is updated every 40 ns. 1 : Port 6 has been partitioned 0 : Port 6 has not been partitioned Status is updated every 40 ns. 1 : Port 5 has been partitioned 0 : Port 5 has not been partitioned Status is updated every 40 ns. 1 : Port 4 has been partitioned 0 : Port 4 has not been partitioned Status is updated every 40 ns. 1 : Port 3 has been partitioned 0 : Port 3 has not been partitioned Status is updated every 40 ns. 1 : Port 2 has been partitioned 0 : Port 2 has not been partitioned Status is updated every 40 ns. 1 : Port 1 has been partitioned 0 : Port 1 has not been partitioned Status is updated every 40 ns. 1 : Port 0 has been partitioned 0 : Port 0 has not been partitioned Status is updated every 40 ns. R/W R R
26.6
PartP6
R
26.5
PartP5
R
26.4
PartP4
R
26.3
PartP3
R
26.2
PartP2
R
26.1
PartP1
R
26.0
PartP0
R
Table 6-9 Partition Status Register Bit Definition
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MX98745
J. Elastic Buffer Over/Underflow Status Register (register #27) (R) Bit(s) 27.15:0 27.7 Name Reserved EBOUF7 Description Always 0. 1 : Elastic Buffer Over/Underflow at Port 7 0 : Normal Condition. Clear to 0 after read. 1 : Elastic Buffer Over/Underflow at Port 6 0 : Normal Condition. Clear to 0 after read. 1 : Elastic Buffer Over/Underflow at Port 5 0 : Normal Condition. Clear to 0 after read. 1 : Elastic Buffer Over/Underflow at Port 4 0 : Normal Condition. Clear to 0 after read. 1 : Elastic Buffer Over/Underflow at Port 3 0 : Normal Condition. Clear to 0 after read. 1 : Elastic Buffer Over/Underflow at Port 2 0 : Normal Condition. Clear to 0 after read. 1 : Elastic Buffer Over/Underflow at Port 1 0 : Normal Condition. Clear to 0 after read. 1 : Elastic Buffer Over/Underflow at Port 0 0 : Normal Condition. Clear to 0 after read. R/W R R
27.6
EBOUF6
R
27.5
EBOUF5
R
27.4
EBOUF4
R
27.3
EBOUF3
R
27.2
EBOUF2
R
27.1
EBOUF1
R
27.0
EBOUF0
R
Table 6-10 Elastic Buffer Over/Underflow Status Register Bit Definition
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MX98745
K. Jabber Status Register (register #28) (R) Bit(s) 28.15:0 28.7 28.6 28.5 28.4 28.3 28.2 28.1 28.0 Name Reserved JABP7 JABP6 JABP5 JABP4 JABP3 JABP2 JABP1 JABP0 Description Always 0. 1 : Receive Jabber Active at Port 7 0 : No Jabber condition at Port 7 1 : Receive Jabber Active at Port 6 0 : No Jabber condition at Port 6 1 : Receive Jabber Active at Port 5 0 : No Jabber condition at Port 5 1 : Receive Jabber Active at Port 4 0 : No Jabber condition at Port 4 1 : Receive Jabber Active at Port 3 0 : No Jabber condition at Port 3 1 : Receive Jabber Active at Port 2 0 : No Jabber condition at Port 2 1 : Receive Jabber Active at Port 1 0 : No Jabber condition at Port 1 1 : Receive Jabber Active at Port 0 0 : No Jabber condition at Port 0 R/W R R R R R R R R R
Table 6-11 Jabber Status Register Bit Definition
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MX98745
L. Isolation Status Register (register #29) (R) Bit(s) 29.15:0 29.7 29.6 29.5 29.4 29.3 29.2 29.1 29.0 Name Reserved ISO7 ISO6 ISO5 ISO4 ISO3 ISO2 ISO1 ISO0 Description Always 0. 1 : Port Isolation is occuring at port 7, 0 : Port Isolation is not occuring at port 7. 1 : Port Isolation is occuring at port 6, 0 : Port Isolation is not occuring at port 6. 1 : Port Isolation is occuring at port 5, 0 : Port Isolation is not occuring at port 5. 1 : Port Isolation is occuring at port 4, 0 : Port Isolation is not occuring at port 4. 1 : Port Isolation is occuring at port 3, 0 : Port Isolation is not occuring at port 3. 1 : Port Isolation is occuring at port 2, 0 : Port Isolation is not occuring at port 2. 1 : Port Isolation is occuring at port 1, 0 : Port Isolation is not occuring at port 1. 1 : Port Isolation is occuring at port 0, 0 : Port Isolation is not occuring at port 0. R/W R R R R R R R R R
Table 6-12 Isolation Status Register Bit Definition
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MX98745
M. Configuration Register (register #31) (R/W) Bit(s) 31.15 31.14 Name Reserved L40H80 Description Reserved for further usage. 1:Internal arbiter will qualify EDENL for more than 80 ns. 0:Internal arbiter will qualify EDENL for more than 40 ns. Power on low. Reserved for further usage. Power on reset value of LDS0. After power on reset, Write 1 to this bit will not make EEPROM operation. When EECF is low, then value on corresponding pins (known as hardwire setting) will be latched by MX98745 and overwrite the default setting of MX98745. Force to High all the time. 1 : Set XRC II to monitor mode and monitor serial output of internal state machine through LED7..0 0 : Put MX98745 in normal mode. 0:Internal Arbitor function is disabled. 1:Internal Arbitor function is enabled Power on low. 1 : Partition function meets IEEE 802.3u i.e. when two ports collide more than 128 times, two ports will be partitoned by MX98745 simultaneously. 0 : Those ports which Receive after Transmit will be partitioned.(Same as MX98741) i.e. ports encounter transmit collision will be paritioned only. Value on LED0 will be stored in this bit in case EECONF is 0. 1:PCS type MII for port0 0:MAC type MII for port0 value on LED1 will be stored at this bit after power on reset. When TXXMII is set to 1, this bit has no effect. Contents will not be overwritten by EEPROM. 1 : TX port is programmed (5B) for port 0 0 : MII mode (4B) is programmed for port 0 After power on reset, value on LED2 will be stored on this bit. Contents will not be overwritten while loading EEPROM. Physical address of MX98745. When EECONF is set to 0 (Disabled), value on LED[7:3] will be stored in these five bits at the rising edge of RESETL. If EECONF is set to high, value from EEPROM will overwrite the hardwire setting. R/W R/W R/W
31.13:12 31.11
Reserved EECF
R
31.10 31.9
Reserved MONITOR
R/W R
31.8
INTARB
R/W
31.7
FLWSPEC
R/W
31.6
PXM
R/W
31.5
TXXMII
R/W
31.4:0
PHY[4:0]
R/W
Table 6-13 Configuration Register Bit Definition
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MX98745
6.4 EEPROM Mapping Word # 5 4 3 2 1 0 Bit 15 .................. 8 MSB of Register #31 MSB of Register #20 MSB of Register #19 MSB of Register #18 MSB of Register #17 MSB of Register #16 7 .......................... 0 LSB of Register #31 LSB of Register #20 LSB of Register #19 LSB of Register #18 LSB of Register #17 LSB of Register #16
7.0 ABSOLUTE MAXIMUM RATINGS
RATING Supply Voltage (VCC) DC Input Voltage (Vin) DC Output Voltage (Vout) Storage Temperature Range (TSTG) Power Dissipation (PD) ESD rating (Rzap = 1.5K, Czap = 100pF) VALUE 4.75V to 5.25V -0.5V to VCC+0.5V -0.5V to VCC+0.5V -55 C to 150 C 750 mW 2000V
Table 7-1 Absolute Maximum Rating for MX98745
Notice : Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cauase permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended period may affect reliability.
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MX98745
8.0 DC Characteristics
SYMBOL PARAMETER A. Supply Current ICC Average Active (TXing/ RXing) Supply Current ICCIDLE Average Idle Supply Current IDD Static IDD Current B. TTL Inputs, Outputs, Tri-States Vil Maximum Low Level Input Voltage Vih Minimum High Level Input Voltage Iin Input Current Voh Minimum High Level Output Voltage (Others/MII/Expansion) Vol Maximum Low Level Output Voltage (Others/MII/Expansion) Ioz Maximum TRI-STATE Output Leakage Current C. CMOS Inputs, Outputs Voh Minimum High Level Output Voltage Vol Maximum Low Level Output Voltage Vil Maximum Low Level Vih Minimum High Level Iin Input Current
CONDITIONS
X1 = 25MHz VIN = Switching X1 = 25MHz VIN=VCC/GND X1=Undriven GND = 0V
MIN.
MAX.
UNIT
-
150 10 600
mA mA uA
2.0 -1.0
0.8 VCC+0.5 1.0
V V uA
VI=VCC/GND Ioh = -2mA/ -4mA/ -8mA Iol = 2mA/ 4mA/ 8mA VOUT=VCC/ GND
2.4
-
V
-10.0
0.4 10.0
V uA
Ioh = -20uA Iol = 20uA Input Voltage Input Voltage VI=VCC/GND
VCC-0.1 -
0.1 0.8 1.0
V V V V uA
2.0 -1.0
Table 8-1 DC Characteristics for MX98745
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MX98745
9.0 AC CHARACTERISTICS AND WAVEFORMS
A. Media Independent Interface
T01 T02 T03
MDC T04 MDIO T05
Figure 9-1 MDIO Timing Relationship MDC
Symbol T01 T02 T03 T04 T05a T05b
Description Period for MDC High Time for MDC Low Time for MDC MDIO Setup to MDC rising edge (sourced by STA) MDIO Hold to MDC rising edge (sourced by STA) MDIO Hold to MDC rising edge (source by XRC)
MIN. 400 160 160 10 10 18
MAX. 25
UNIT ns ns ns ns ns ns
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MX98745
T11 T12 T13
RSCLK0 T14 RXD[3:0] RXDV RXER T15
Figure 9-2 Receive Signal Timing Relationships for MII mode
Symbol T11 T12 T13 T14 T15
Description RSCLK0 Period (Note 1) RSCLK0 High Time RSCLK0 Low Time RXD[3:0]/RXDV/RXER Setup Time to RSCLK0 rising edge (Note 2) RXD[3:0]/RXDV/RXER Hold Time to RSCLK0 rising edge (Note 2)
MIN. 40 10 7 10 10
MAX. 40 -
UNIT ns ns ns ns ns
Note 1 : The accurate RSCLK frequency shall be 25 MHz +/- 50 ppm. Note 2 : The setup time of an MII signal relative to an MII clock edge is defined as the length of time between when the signal exits and remains out of the switching region and when the clock enters the switching region. The hold time of an MII signal relative to an MII clock edge is defined as the length of time between when the clock exits the switching region and when the signal enters the switching region.
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MX98745
T21 T22 T23
TXCLK T24 TXD[3:0] TXEN TXER T25
Figure 9-3 Trannsmit Signal Timing Relationships at the MII
Symbol T21 T22 23 T24 T25
Description TXCLK Period (Note 1) TXCLK High Time TXCLK Low Time TXD[3:0]/TXEN/TXER Setup Time to TXCLK rising edge (Note 2) TXD[3:0]/TXEN/TXER Hold Time to TXCLK rising edge (Note 2)
MIN. 40 20 18 20 15
MAX. 40 -
UNIT ns ns ns ns ns
Note 1 : The accurate TXCLK frequency shall be 25 MHz +/- 50 ppm. In PCS type MII, this signal is outputed by MX9745. In MAC type MII, this signal is input to MX98745. Note 2 : The setup time of an MII signal relative to an MII clock edge is defined as the length of time between when the signal exits and remains out of the switching region and when the clock enters the switching region. The hold time of an MII signal relative to an MII clock edge is defined as the length of time between when the clock exits the switching region and when the signal enters the switching region. (see section 22.3 in [1])
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MX98745
B. Data Transceiver Interface
LSCLK T31 TDAT[4:0]
Figure 9-4 Trannsmit Signal Timing Relationships at the DT
Symbol T31
Description TDAT[4:0] to LSCLK Delay Time
MIN. 10
MAX. 15
UNIT ns
Note : Tested under 30pF loading.
T41 T42 T43
RSCLK T44 RDAT[4:0] T45
Figure 9-5 Receive Signal Timing Relationships at the DT
Symbol 41 T42 T43 T44 T45
Description RSCLK Period (Note 1) RSCLK Pulse Width High RSCLK Pulse Width Low Time RDAT[4:0] Valid to RSCLK Rise RSCLK Rise to RDAT[4:0] Invalid
MIN. 40 11 20 2 4
MAX. 40 -
UNIT ns n ns ns ns
Note 1 : The accurate RSCLK frequency shall be 25 MHz +/- 50 ppm.
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MX98745
RESETL
T51
Figure 9-6 Timing Constraint RESEL
Symbol T51
Description Pulse Width for RESETL
MIN. 800
MAX. -
UNIT us
Note : RESETL must keep active low until LSCLK is stable more than 200 us.
C. Expansion Port Interface
LSCLK
ANYACT
T71
EDENL
T72
T73
EDACT
Figure 9-7 Expansion Port with One port activates
Symbol T71 T72 T73
Description ANYACT asserted to EDENL asserted (Note 3) LSCLK rising to EDACT asserted (Note 1, 2) LSCLK rising to EDACT deassert
MIN.
MAX. 80 20 20
UNIT ns ns ns
Note 1 : EDENL will be filtered by 2 LSCLK clock within MX98745. Whenever MX98745 detects EDENL, it will assert EDACT at the rising edge of LSCLK Note 2 : Expansion port data will be released onto EDAT[4:0] at the next LSCLK rising edge right after EDACT is asserted which is not shown in this figure. Note 3 : ANYACT has not any timing relationship to LSCLK in MX98745. i.e. it is asynchronous to LSCLK.
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MX98745
LSCLK
ANYACT1
ANYACT2
EDENL1
T81
EDENL2
EDACT1
T82
JAMI T83 JAMO1
Figure 9-8 Expansion Port with Collision (Note 1)
Symbol T81 T82 T83
Description Valid EDENL duration to make EDACT active Collision Condition to JAMI asserted (Note 2) JAMO asserted to JAMI asserted (Note 3)
MIN. 80
MAX. 10 10
UNIT ns ns ns
Note 1 : EDENL2 asserted after collision will not make EDACT2 assert in MX98745 due to MX98745 will mask activity from expansion port from ces sation of collision to cessation of ANYACT2. Note 2 : Deassert timing is the same Note 3 : Deassert timing is the same. Either T72 or T73 should cause JAMI assert Note 4 : EDENL, JAMI and EDCRS (not shown in this timing) should be filtered by LSCLK to resolve asynchronous issue.
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MX98745
EPCLK T91 EDAT /I/ /J/ /K/ /D1/ T92 /T/ T93 /R/
Figure 9-9 EPCLK and EDAT Timing Relationship
Symbol T91 T92 T93
Description EPCLK to EDAT delay time (EPCLK and EDAT outputed from MX98745) EDAT Setup Time (Input to MX98745) EDAT Hold Time (Input to MX98745)
MIN. 12 5 5
MAX. 16 -
UNIT ns ns ns
D. LED Display
T96
LEDEN T97 LDS2_0 T99 LED7_0 T100 T98
Figure 9-10 Timing Relationship for LED Display
Symbol T96 T97 T98 T99 T100
Description LEDEN Period LDS2_0 Setup Time LDS2_0 Hold Time LED7_0 Setup Time LED7_0 Hold Time
MIN. 9.9 4.0 4.9 4.0 4.9
MAX. 10.1 -
UNIT ms ms ms ms ms
Note : Where LED7_0 definition relative to LDS2_0 configuration, please reference pin description of LDS2_0
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MX98745
10.0 PACKAGE INFORMATION
160-PIN PLASTIC QUAD FLAT PACK
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MX98745
HISTORY OF CHANGE MADE
Rev. No. 1.1 1.2 1.3 Description P 1, 9, 10, 11:Change scale for utilization and collision rate LED display. P28:Change configuration register (register #31) description. P30:Change 7.0 ABSOLUTE MAXIMUM RATINGS:Power Dissipation, from 1500mw to 750mw. P30:Change 8.0 DC Characteristics:ICC(MAX.), form 300mA to 150mA. P2:Change expansion port signal name from EPCLK to ANYACT. Date JAN. 31, 1997 MAR. 12, 1997
1.4
JUL. 03, 1997 JUL. 10, 1998
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MX98745
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